ISMVL 2015
IEEE International Symposium
on Multiple-Valued Logic
Quantum Nano Centre Math Building Uptown

Source: University of Waterloo website

Final Program

Monday, May 18, 2015
9:00-10.00 [Keynote Address I] Chair: F. Manyà                         Room: Main Hall
Algebras and Algorithms
Matt Valeriote (McMaster University, Canada)
10:30-12:00 [1A. Reversible Logic I]
Chair: M. Soeken       Room: MPR A
[1B. Algebra I]
Chair: M. Couceiro     Room: MPR B
Reversible Logic Synthesis via Biconditional Binary Decision Diagrams
A. Chattopadhyay, A. Littarru, L. Amarú, P.-E. Gaillardon, and G. De Micheli
Quotient Structures of Non-Commutative Residuated Lattices
M. Kondo
Online Testing for Three Fault Models in Reversible Circuits
M. A. Nashiry, G. G. Bhasker, and J. E. Rice
Cut-Down Operations on Bilattices
T. M. Ferguson
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization
A. Deb, R. Wille, R. Drechsler, and D. K. Das
Finding Hard Instances of Satisfiability in Łukasiewicz Logics
M. Bofill, F. Manyà, A. Vidal, and M. Villaret
13:30-14:30 [2A. Quantum Computing]
Chair: C. Moraga       Room: MPR A
[2B. Circuits over Galois Fields]
Chair: T. Waho           Room: MPR B
Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing
N. J. Lisa and H. M. H. Babu
Formal Design of Galois-Field Arithmetic Circuits Based on Polynomial Ring Representation
R. Ueno, N. Homma, Y. Sugawara, and T. Aoki
An Examination of the NCV-|v1> Quantum Library Based on Minimal Circuits
A. A.-Abhari, R. Wille, and R. Drechsler
System for Automatic Generation of Parallel Multipliers over Galois Field
Y. Sugawara, R. Ueno, N. Homma, and T. Aoki
15:00-16:30 [3A. Reversible Logic II]
Chair: J. Rice             Room: MPR A
[3B. Algebra II]
Chair: H. Machida       Room: MPR B
Fredkin-Enabled Transformation-Based Reversible Logic Synthesis
M. Soeken and A. Chattopadhyay
Standard Completeness for Uninorm-Based Logics
P. Baldi and A. Ciabattoni
Single-Electron Transistor Based Implementation of NOT, Feynman, and Toffoli Gates
M. H A Khan
Hereditarilyy Rigid Relations
M. Couceiro, L. Haddad, M. Pouzet, and K. Schölzel
Dynamic Template Matching with Mixed-Polarity Toffoli Gates
M. M. Rahman, M. Soeken, and G. W. Dueck
Valuations in Nilpotent Minimum Logic
P. Codara and D. Valota
Tuesday, May 19, 2015
9:00-10:00 [Keynote Address II] Chair: D. M. Miller                     Room: Main Hall
Contextuality Supplies the Magic for Quantum Computation
Mark Howard, Joel Wallman (University of Waterloo, Canada), Victor Veitch (University of Toronto, Canada), and Joseph Emerson (University of Waterloo, Canada)
10:30-12:00 [4A. Application-Specific Circuits]
Chair: N. Homma       Room: MPR A
[4B. Data Mining]
Chair: B. Steinbach   Room: MPR B
An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD
H. Nakahara, T. Sasao, H. Nakanishi, and K. Iwai
A Novel Weighted Hierarchical Adaptive Voting Ensemble Machine Learning Method for Breast Cancer Detection
C. Deng and M. Perkowski
Non-Binary Analog-to-Digital Converter Based on Amoeba-Inspired Neural Network
U. Ishida, Y. Yamazaki, and T. Waho
Computation Time Reduction to Speed-up the Database Searching Process
T. Bonny and B. Soudan
Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors
D. Katagiri, N. Onizawa, and T. Hanyu
Grading Evaluation Method in Character Drawing Study Support System
R. Murakami and N. Muranaka
Wednesday, May 20, 2015
9:00-10:00 [Keynote Address III] Chair: T. Hanyu                       Room: Main Hall
Novel VLSI Architectures for Real-World Intelligent Systems
Michitaka Kameyama (Tohoku University, Japan)
10:30-12:00 [5A. Logic and Stateflow Models]
Chair: T. Sasao         Room: MPR A
[5B. Memory Circuits]
Chair: V. Gaudet       Room: MPR B
Contribution to the Study of Ternary Functions with a Bent Reed-Muller Spectrum
C. Moraga, M. Stanković, and R. S. Stanković
Write-Operation Frequency Reduction for Nonvolatile Logic LSI with a Short Break-Even Time
T. Akutsu, M. Natsui, and T. Hanyu
Towards Fuzzy Partial Logic
L. Běhounek and V. Novák
A Multi-Level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction
A. Vatankhahghadim and A. Sheikholeslami
Using SPIN to Check Nondeterministic Simulink Stateflow Models
C. Yamada and D. M. Miller
13:30-15:30 [6A. Decision Diagrams]
Chair: R. Wille           Room: MPR A
[6B. Clones]
Chair: L. Haddad       Room: MPR B
A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method
T. Sasao
Bounded Bases of Strong Partial Clones
V. Lagerkvist, M. Wahlström, and B. Zanuttini
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-State Systems
S. Nagayama, T. Sasao, J. T. Butler, M. A. Thornton, and T. W. Manikas
Clones of Pivotally Decomposable Functions
M. Couceiro and B. Teheux
Belief Network Support via Decision Diagrams
S. C. Eastwood, S. N. Yanushkevich, and V. P. Shmerko
Lazy Clones and Essentially Minimal Groupoids
H. Machida and T. Waldhauser
Using QMDD in Numerical Methods for Solving Linear Differential Equations via Walsh Functions
R. S. Stanković and D. M. Miller
Some Classes of Centralizing Monoids on a Three-Element Set
M. Goldstern, H. Machida, and I. G. Rosenberg
16:00-17:00 Plenary Session & Closing
Room: MPR A

Brief Map of Federation Hall

Schedule of Shuttles to and from Hotels

Sunday, May 17, 2015
To Hotels
19:00 Departure from Federation Hall
(after the Welcome Reception)
19:10 Ron Edyt Village
(a regidence at University of Waterloo)
19:25 Delta Hotel in Waterloo
Monday, May 18, 2015
From Hotels
7:30 - 7:45 Departure from Delta Hotel
7:55 - 8:05 Ron Edyt Village
8:15 Federation Hall
To Hotels
16:30 - 16:45 Departure from Federation Hall
16:55 Ron Edyt Village
17:05 Delta Hotel
Tuesday, May 19, 2015
From Hotels
8:00 - 8:15 Departure from Delta Hotel
8:25 - 8:35 Ron Edyt Village
8:40 Federation Hall
Wednesday, May 20, 2015
From Hotels
8:00 - 8:15 Departure from Delta Hotel
8:25 - 8:35 Ron Edyt Village
8:40 Federation Hall
To Hotels
17:00 - 17:15 Departure from Federation Hall
17:25 Ron Edyt Village
17:35 Delta Hotel

The Technical Committee on Multiple-Valued Logic of the IEEE Computer Society held its 45th annual symposium in Waterloo, Ontario, Canada, from May 18 to 20, 2015.

The program consists of three invited talks and 35 high-quality papers. It offers you a great opportunity to follow the recent technologies and explore future directions in multiple-valued logic and its related areas.

Final Program

Download complete Program