Graduate School of Information Science and Technology,
Hokkaido University
ISMVL 2016
IEEE International Symposium
on Multiple-Valued Logic
Ski Jump  Clock Tower  Downtown

Final Program

Tuesday, May 17, 2016
9:00- ISMVL Registration                                                       Entrance Hall
10:00- Post-Binary ULSI Workshop                                     Seminar Room 1
18:00- Reception                                             Kogakubu Shokudo (Cafeteria)
Wednesday, May 18, 2016
9:00-9:15 Opening                                                 Room: Akira Suzuki Hall (ASH)
9:15-10:00 [Keynote Address I] Chair: T. Hanyu                                 Room: ASH
Elucidation of Brain Activities by Electroencephalograms and its Application to Brain Computer Interface
Takahiro Yamanoi (Hokkai-Gakuen University, Japan)
10:20-12:00 [1A. Circuits I]
Chair: M. Natsui           Room: ASH
[1B. Synthesis of Reversible Circuits] Chair: R. Wille
        Room: Seminar Room 2 (SR2)
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme
D. Suzuki and T. Hanyu
Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits
Z. Alwardi, R. Wille, and R. Drechsler
CNTFET-RFB: An Error Correction Implementation For Multi-Valued CNTFET Logic
G. Sundararajan and C. Winstead
An Improved Factorization Approach to Reversible Circuit Synthesis Based on EXORs of Products of EXORs
L. Tran, A. Gronquist, M. Perkowski, and J. Caughman
Ternary versus Binary Multiplication with Current-Mode CNTFET-based K-Valued Converters
M. Moradi, R. F. Mirzaee, and K. Navi
Fault Detection in Parity Preserving Reversible Circuits
N. Przigoda, G. Dueck, R. Wille, and R. Drechsler
Design of Ratioless Ternary Inverter using Graphene Barristor
C.-H. Shim, S. Heo, J. Noh, Y. J. Kim, S.-Y. Kim, A. K. Khan, and B. H. Lee
Notes on Majority Boolean Algebra
A. Chattopadhyay, L. Amaru, M. Soeken, P.-E. Gaillardon, and G. De Micheli
12:00-13:20 Lunch (Symposium Committee)               Hokubu Shokudo (Cafeteria)
13:20-14:05 [Keynote Address II] Chair: M. F. Kawaguchi                     Room: ASH
Realization of Associative Image Search: Development of Image Retrieval Platform for Enhancing Serendipity
Miki Haseyama (Hokkaido University, Japan)
14:20-15:35 [2A. Circuits II]
Chair: N. Homma         Room: ASH
[2B. Clone]
Chair: D. Simovici         Room: SR2
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope
H. Nakahara, T. Sasao, H. Nakanishi, K. Iwai, T. Nagao, and N. Ogawa
Monomial Clones: Local Results and Global Properties
H. Machida and J. Pantovic
Double-Rate Equalization Using Tomlinson-Harashima Precoding for Multi-Valued Data Transmission
Y. Iijima and Y. Yuminaka
Centralizing Monoids on a Three-Element Set Related to Binary Idempotent Functions
H. Machida and I. G. Rosenberg
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission
N. Sugaya, M. Natsui, and T. Hanyu
Minimal Weighted Clones with Boolean Support
P. G. Jeavons, A. Vaicenavicius, and S. Zivny
15:50-17:30 [3A. Index Generation Functions]
Chair: Y. Iguchi             Room: ASH
[3B. Algebra I]
Chair: F. Manya             Room: SR2
An Efficient Heuristic for Linear Decomposition of Index Generation Functions
S. Nagayama, T. Sasao, and J. T. Butler
Set Representation of Partial Dynamic De Morgan Algebras
I. Chajda and J. Paseka
Index Generation Functions based on Linear and Polynomial Transformations
H. Astola, R. Stankovic, and J. Astola
Tolerance Distances on Minimal Coverings
C. Zara and D. A. Simovici
An Algebraic Approach to Reducing the Number of Variables of Incompletely Defined Discrete Functions
J. Astola, P. Astola, R. Stankovic, and I. Tabus
Paraconsistent Double Negation That Can Simulate Classical Negation
Norihiro Kamide
A Realization of Index Generation Functions Using Multiple IGUs
T. Sasao
Cut-Free Systems for Restricted Bi-Intuitionistic Logic and Its Connexive Extension
Norihiro Kamide
Thursday, May 19, 2016
9:15-10:00 [Keynote Address III] Chair: T. Sasao                               Room: ASH
Power of Enumeration --- BDD/ZDD-Based Techniques for Discrete Structure Manipulation
Shin-ichi Minato (Hokkaido University, Japan)
10:20-11:35 [4A. From Reversible to Quantum Circuits]
Chair: M. Lukac             Room: ASH
[4B. Algebra II]
Chair: J. Paseka           Room: SR2
Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits
M. M. Rahman, G. W. Dueck, A. Chattopadhyay, and R. Wille
Some Properties of Generalized State Operators on Residuated Lattices
M. Kondo and M. F. Kawaguchi
Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits
N. Abdessaied, M. Amy, M. Soeken, and R. Drechsler
Simple Characterizations of Perfect Residuated Lattices
M. Kondo
Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation
L. Biswal, C. Bandyopadhyay, A. Chattopadhyay, R. Wille, R. Drechsler, and H. Rahaman
11:40- Excursion with Lunch
19:00- Banquet
Friday, May 20, 2016
9:15-10:00 [Keynote Address IV] Chair: Y. Yuminaka                         Room: ASH
SPRUCE, an Embedded Compact Stack Machine for IGBT Power Modules
Wai Tung Ng and Andrew Shorten (University of Toronto, Canada)
10:15-12:20 [5A. Intelligent Medical and Welfare Engineering]
Chair: T. Araki             Room: ASH
[5B. Logic I]
Chair: S. Nagayama       Room: SR2
Gray-Scale Morphology Based Image Segmentation and Character Extraction Using SVM
J. Chen and N. Takagi
Gibbs Characterization of Binary and Ternary Bent Functions
R. S. Stankovic, M. Stankovic, J. T. Astola, and C. Moraga
A Low-Voltage and Low-Power CMOS Temperature Sensor Circuit with Digital Output for Wireless Healthcare Monitoring System
A. Setiabudi, R. Sakamoto, H. Tamura, and K. Tanno
On Constructing Secure and Hardware-Efficient Invertible Mappings
E. Dubrova
Dependency Analysis of BMI in Health Checkup Blood Data
M. Higuchi, K. Sorachi, and Y. Hata
Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors
R. Ueno, Y. Sugawara, N. Homma, and T. Aoki
Novel Instrumentation Amplifier Architectures Insensitive to Resistor Mismatches and Offset Voltage for Biological Signal Processing
Z. Abidin, K. Tanno, S. Mago, and H. Tamura
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation
S. Koshita, N. Onizawa, M. Abe, T. Hanyu, and M. Kawamata
Study Support System of Character Drawing considering Feeling Evaluation
R. Murakami and N. Muranaka
The Pascal triangle (1654), the Reed-Muller-Fourier Transform (1992), and the Discrete Pascal Transform (2005)
C. Moraga, R. Stankovic, and M. Stankovic
12:20-13:40 Lunch (Executive Committee)                  Hokubu Shokudo (Cafeteria)
13:40-15:20 [6A. Quantum Gates and Quantum States]
Chair: G. Dueck            Room: ASH
[6B. Logic II]
Chair: R. Stankovic       Room: SR2
New Two-Qubit Gate Library with Entanglement
M. B. Ali, T. Hirayama, K. Yamanaka, and Y. Nishitani
A Study on Realizing Awareness Using 3VL-MLP
Q. Zhao
Quantum p-Valued Toffoli and Deutsch Gates with Conjunctive or Disjunctive Mixed Polarity Control
C. Moraga
Multi-Valued Problem Solvers
B. Steinbach, S. Heinrich, and C. Posthoff
Logic Synthesis for Quantum State Generation
P. Niemann, R. Datta, and R. Wille
A Bit-Vector Approach to Satisfiability Testing in Finitely-Valued Logics
J. R. Soler and F. Manya
Quantum Algorithmic Complexity of Three-Qubit Pure States
M. Lukac and A. Mandilara
On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults
D. Chowdhury, D. K. Das, B. B. Bhattacharya, and T. Sasao
15:30-17:00 Plenary Session & Closing                                                     Room: ASH

Brief Map of the Building

Brief Map for Reception & Lunch (Outside the Building)

The Technical Committee on Multiple-Valued Logic of the IEEE Computer Society will hold its 46th annual symposium in Sapporo, Japan, from May 18 to 20, 2016.

The program consists of four invited talks and 45 high-quality papers. It offers you a great opportunity to follow the recent technologies and explore future directions in multiple-valued logic and its related areas.

Final Program

Download PDF file