ISMVL 2016, May 18-20, 2016, Sapporo, Japan
Thank You for Attending!
See You Next Year in
Novi Sad, Serbia.
Photos at ISMVL 2016:
- Photos kindly provided by Prof. Yuminaka at Gunma University, Japan.
The Technical Committee on Multiple-Valued
Logic of the IEEE Computer Society will hold its 46th annual
symposium in Sapporo, Japan, on May 18-20, 2016.
The symposium will bring together researchers from computer science, engineering, mathematics, and further
disciplines to discuss new
developments and directions for future research in the area of multi-valued logic and related fields.
Research papers, surveys, or tutorial papers on any subject in these areas are within the scope of the symposium.
The following keynote speakers will present their cutting-edge
- Prof. Wai Tung Ng (University of Toronto, Canada)
SPRUCE, an Embedded Compact Stack Machine for IGBT Power Modules
- Prof. Takahiro Yamanoi (Hokkai-Gakuen University, Japan)
Elucidation of Brain Activities by Electroencephalograms and its Application to Brain Computer Interface
- Prof. Shin-ichi Minato (Hokkaido University, Japan)
Power of Enumeration --- BDD/ZDD-Based Techniques for Discrete Structure Manipulation
- Prof. Miki Haseyama (Hokkaido University, Japan)
Realization of Associative Image Search: Development of Image Retrieval Platform for Enhancing Serendipity
» IEICE Transactions Special Section on MVL and VLSI
Call for Papers
(Aug. 3, 2016).
» Photos at ISMVL 2016 are available (May 24, 2016).
» ISMVL 2016 has successfully done.
» Presentation Guideline was added on May 2, 2016.
» Final Program was added on April 21, 2016.
» The page for Social Events was added on Mar. 15, 2016.
» Titles of Invited Talks were added on Mar. 15, 2016.
» Information on hotels was added on Feb. 12, 2016.
» This site was open on May 15, 2015.
» Paper Submission Deadline:
November 2, 2015 (extended!)
November 30, 2015
» Notification of Acceptance:
February 1, 2016
» Camera-Ready Version:
March 1, 2016
» Early Registration Deadline:
April 10, 2016
May 18-20, 2016